The complexity of modern chip design requires extensive use of specialized software throughout the process. To achieve the best results, a user of this software needs a high-level understanding of the underlying mathematical models and algorithms. In addition, a developer of such software must have a keen understanding of relevant computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. This book introduces and compares the fundamental algorithms that are used during the IC physical design phase, wherein a geometric chip layout is produced starting from an abstract circuit design. This updated second edition includes recent advancements in the state-of-the-art of physical design, and builds upon foundational coverage of essential and fundamental techniques. Numerous examples and tasks with solutions increase the clarity of presentation and facilitate deeper understanding. A comprehensive set of slides is available on the Internet for each chapter, simplifying use of the book in instructional settings.

“This improved, second edition of the book will continue to serve the EDA and design community well. It is a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools and design the most advanced micro-electronics.”

Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Systems Group

“This is the book I wish I had when I taught EDA in the past, and the one I’m using from now on.”

Dr. Louis K. Scheffer, Howard Hughes Medical Institute

“I would happily use this book when teaching Physical Design. I know of no other work that’s as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!”

Prof. John P. Hayes, University of Michigan

“The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.”

Prof. Kurt Keutzer, University of California, Berkeley

“An excellent balance of the basics and more advanced concepts, presented by top experts in the field.”

Prof. Sachin Sapatnekar, University of Minnesota

Table of Contents

1: Introduction

2: Netlist and System Partitioning

3: Chip Planning

4: Global and Detailed Placement

5: Global Routing

6: Detailed Routing

7: Specialized Routing

8: Timing Closure

9: Appendix

About the Authors

Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006).

Jens Lienig is Professor of Electrical Engineering at TU Dresden. He is also the director of the Institute of Electromechanical and Electronic Design at TUD. He has worked as project manager at Tanner Research, Inc. (1996-1999) and Robert Bosch GmbH (1999-2002).

Igor L. Markov is a Fellow of IEEE and an ACM Distinguished Scientist. In addition to his career as a Professor of Electrical Engineering and Computer Science at the University of Michigan, he has worked at Google (2014-2017) and has been with Facebook since 2018.

Jin Hu was a PhD student at the Computer Science and Engineering (CSE) Division at the University of Michigan. Afterwards, she has been with IBM Corp. (2013-2017), Bloomberg L.P. (2017-2019) and Two Sigma Insurance Quantified (TSIQ) (since 2019).