This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.

Table of Contents

Chapter 1: Basics of Test and Role of HDLs

Chapter 2: Verilog HDL for Design and Test

Chapter 3: Fault and Defect Modeling

Chapter 4: Fault Simulation Applications and Methods

Chapter 5: Test Pattern Generation Methods and Algorithms

Chapter 6: Deterministic Test Generation Algorithms

Chapter 7: Design for Test by Means of Scan

Chapter 8: Standard IEEE Test Access Methods

Chapter 9: Logic Built-in Self-test

Chapter 10: Test Compression

Chapter 11 : Memory Testing by Means of Memory BIST

Appendix A Using HDLs for Protocol Aware ATE1

Appendix B Gate Components for PLI Test Applications

Appendix C Programming Language Inte rface Test Utilities

Appendix D IEEE Std. 1149.1 Boundary Scan Verilog Description

Appendix E Boundary Scan IEEE std. 1149.1 Virtual Tester

Appendix F Generating Netlist by Register Transfer LevelSynthesis (NetlistGen)

About the Author

Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.